The present invention relates to the field of communications, and, more particularly, to phased array antennas and element control devices therefor.
Antenna systems are widely used in both ground based applications (e.g., cellular antennas) and airborne applications (e.g., airplane or satellite antennas). For example, so-called xe2x80x9csmartxe2x80x9d antenna systems, such as adaptive or phased array antennas, combine the outputs of multiple antenna elements with signal processing capabilities to transmit and/or receive communications signals. As a result, such antenna systems can vary the transmission or reception pattern of the communications signals in response to the signal environment to improve performance characteristics.
In such antennas, one or more antenna elements are typically controlled by a phase shifter, attenuator, delay generator, etc., which in turn are controlled by element control circuitry. Such element control circuitry may be implemented in an application specific integrated circuit (ASIC), for example, which may be housed within an element module along with RF control devices such as phase shifters, attenuators, delay generators, amplifiers, etc. The control ASIC provides an interface between the array controller and these RF control devices.
One problem that may be encountered when using ASICs is ensuring that a control ASIC does not suffer from design or manufacturing defects that will affect its operation. ASIC testers are therefore commonly used to determine whether the ASIC design provides the intended result, and whether the ASIC was implemented properly during manufacture.
An example of an ASIC tester is disclosed in U.S. Pat. No. 5,243,274 to Kelsey. The tester includes a microprocessor and a test vector random access memory (RAM) bank on a test board. The RAM bank stores the vector information for the device under test (DUT) input/output pins. In addition, the test also includes several test ASICs located on the test board between the RAM bank and the DUT. The test ASICs are configurable with respect to the particular DUT to control the direction of the data lines and to compare the results of the DUT with pre-loaded RAM data.
Some ASICs are also designed to include self-testing capabilities. For example, output signals may be written to an output register, which in turn outputs the signals from the ASIC. Data written to the output register is internally fed back within the ASIC die to control logic for fault determination. Yet, while such internal test methodology may be used to determine whether the correct data is being provided to the output drivers, it does not determine whether faults have occurred at the ASIC driver outputs or xe2x80x9cdownstreamxe2x80x9d therefrom. For example, output faults, such as an open or short circuit, which may occur along the signal path from the output drivers to the output bonding pads of the control ASIC to the output terminals of the ASIC""s packaging may well go undetected when using only a conventional ASIC self-test. Another problem is that ASIC built-in self-tests typically require that the ASIC cease normal operation to diagnose faults.
In view of the foregoing background, it is therefore an object of the invention to provide a phased array antenna and associated methods which provides fault detection of element control device ASICs.
This and other objects, features, and advantages in accordance with the present invention are provided by a phased array antenna which may include a substrate and a plurality of phased array antenna elements carried thereby and an element control device for at least one of said phased array antenna elements. Each element control device may include an IC die comprising output circuitry, readback circuitry, and control circuitry connected to the output and readback circuitry. The element control device may further include an IC package surrounding the IC die, a plurality of output terminals connected to the output circuitry and extending outwardly from the IC package, and a plurality of readback input terminals connected to the readback circuitry and extending outwardly from the IC package. Further, respective external readback connections may extend between the plurality of output terminals and the plurality of readback input terminals. The control circuitry may cause the output circuitry to output signals on the plurality of output terminals. This is done so that the readback circuitry reads back the output signals via the external readback connections and the plurality of readback input terminals for fault detection.
More specifically, the control circuitry may generate fault detection signals based upon comparing output signals to readback signals. For example, the output signals may be a test pattern sequence during off-line testing, or normal commanded values for testing during normal on-line operation. The phased array antenna may further include an array controller connected to the element control device for receiving fault detection signals therefrom, and the array controller may optionally shut off the element control device based upon a fault detection signal received therefrom. Alternately, the array controller may compare respective output signals to readback signals for fault detection and optionally shut off the element control device based thereon. The array controller may also send output signals to the element control device. More particularly, the array controller may periodically send the output signals to the element control device.
Furthermore, the output circuitry may include at least one register, and the readback circuitry may also include at least one register. The IC die may include a plurality of output bond pads and a plurality of readback input bond pads, and the element controller may also include respective bond wires extending between the output bond pads and the output terminals and between the readback input bond pads and the readback input terminals.
The IC die may be an ASIC, for example. Also, the output signals may be digital output signals. Each of the output terminals may include an electrically conducting lead, and each of the readback input terminals may also include an electrically conducting lead. Additionally, the element control device may also include RF control devices, such as phase shifters, attenuators, delay generators, amplifiers, etc., connected to the plurality of output terminals.
Another aspect of the invention relates to an element control device for an antenna element of a phased array antenna. The element control device may include an IC die comprising output circuitry, readback circuitry, and control circuitry connected to the output and readback circuitry. The element control device may also include an IC package surrounding the IC die, a plurality of output terminals connected to the output circuitry and extending outwardly from the IC package, and a plurality of readback input terminals connected to the readback circuitry and extending outwardly from the IC package. The plurality of output terminals are to be connected to respective readback terminals via external readback connections. Further, the control circuitry may cause the output circuitry to output signals on the plurality of output terminals. This is done so that the readback circuitry reads back the output signals via the external readback connections and the plurality of readback input terminals for fault detection. For example, the output signals may be a test pattern sequence (generated by the control circuitry) during off-line testing, or normal commanded values for testing during normal on-line operation.
A method aspect of the invention is for testing an element control device for an antenna element of a phased array antenna. The element control device may be as described above. The method may include connecting the plurality of output terminals to respective readback terminals using external readback connections, causing the output circuitry to output signals on the plurality of output terminals, and reading back the output signals via the external readback connections and the plurality of readback input terminals using the readback circuitry. Further, fault detection may be performed by comparing output signals to readback signals.